This course covers the use of verilog hdl in high-level synthesis of digital system designs. The language verilog hdl as well as how it is used for describing, modeling, simulating and synthesizing various digital modules will be addressed.
DurationThis course covers the use of verilog hdl in high-level synthesis of digital system designs. The language verilog hdl as well as how it is used for describing, modeling, simulating and synthesizing various digital modules will be addressed.
Verilog HDL coding and synthesis issues on combinational and sequential modules including Finite State Machine will be discussed. In the hands-on sessions, the participants will not only learn the language through hands-on coding, synthesis and simulation of some practical designs, but they will also synthesize and test the designs with industrial software packages and FPGA devices.
Pre-requisition:
Course Outline
Established in 1997, St. Hua Private School specializes in the provision of technical education in information technology, digital graphics design, mechanical engineering and electronics engineering.
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