SystemVerilog Fundamentals for Digital Systems Design

This 14-hour course focuses on the fundamental aspects of systemverilog, including basic structures and constructs, modeling styles, memory design, and finite state machines, with practical examples in each of these topics. The course also covers verification techniques using testbenches, as well as a hands-on tutorial using an electronic design automation (eda) tool from amd-xilinx. 

SystemVerilog hardware description language, standardized as IEEE 1800, is commonly used in the integrated circuit design industry for the design and verification of digital systems.

This course is the first part of three micro-credential courses that enable credit transfer to a UTM Master's program, subject to successful assessments. How to register and make the payment?

This course is split into two sections:

• Class of 2024- Students
• Class of 2024- Professional

When registering, students need to choose and type the number of matric cards or work IDs before they can enroll.

What You Will Learn
Course outcomes

• Describe basic constructs and structures in SystemVerilog
• Design basic digital circuits using the different modeling styles in SystemVerilog
• Design memory systems and finite state machines in SystemVerilog from a given specification
• Write SystemVerilog testbenches and perform functional verification

This course is the first part of three micro-credential courses that enable credit transfer for MKEL 1283 Hardware and Software Co-Design.

• Part-1: SystemVerilog Fundamentals for Digital Systems Design
• Part-2: Register Transfer Level Design and Optimization with SystemVerilog
• Part-3: Using Vivado High-level Synthesis for Rapid Prototyping

Course Overview

This course consists of lecture notes, lecture videos, learning module and assessment

• Module 1: Introduction to Digital Systems Design and SystemVerilog
• Module 2: SystemVerilog Basic Constructs
• Module 3: SystemVerilog Modeling Styles
• Module 4: SystemVerilog Sequential Logic
• Module 5: SystemVerilog Parameterization and Memory Design
• Module 6: SystemVerilog Finite State Machine
• Module 7: SystemVerilog Testbench Design
• Module 8: SystemVerilog with Xilinx Vivado

Pre-Requisite Knowledge

• Basic knowledge in digital electronics and/or systems