TCL Scripting

by VLSIGuru Claim Listing

TCL scripting is much sought-after skill set for every VLSI engineer. Training will provide the detailed practical exposure on each aspect of project flow setup mostly focused on Physical Design, STA, and functional verification with multiple hands on examples.

£7500

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Course Details

TCL scripting is much sought-after skill set for every VLSI engineer. Training will provide the detailed practical exposure on each aspect of project flow setup mostly focused on Physical Design, STA, and functional verification with multiple hands on examples.

TCL training is for VLSI professionals and students who work on Synopsys tools like ICC/ICC2 Compiler, DFT Compiler, Design Compiler , Primetime. Training will enhance your scripting skills which increase your productivity while using Synopsys tools.

Real time Projects/Assignments will be given to audience as well as driven by audience requirements. Explanation and Execution of all concepts, commands and scripts will done in ICC shell to connect to audience requirements. VPN will be given to audience for practice and execution of projects/assignments. Tools Used for TCL Scripting : ICC2, Primetime, Design Compiler

All the EDA tool flows from Synopsys, Cadence and Mentor Graphics use Tcl as the primary scripting interface for their flows. TCL as a single command language in all EDA tool flows ensures that a designer only needs to learn Tcl in order to work with all the flows.

TCL scripting is much sought after skill set for every VLSI engineer. Training will provide the detailed practical exposure on each aspect of project flow setup mostly focused on Physical Design, STA, and functional verification with multiple hands on examples.


Syllabus:

  • Basics of TCL
  • Overview
  • Env Setup
  • Special Variables
  • Data Types
  • Variables
  • Operators
  • Decisions
  • Loops
  • Arrays, Strings, Lists, Dictionary
  • History and Redoing of commands
  • String Pattern Matching commands
  • Working with files – open, write, read, append
  • Regular expressions
  • Parsing VHDL code to Verilog code
  • Application oriented TCL
  • Projects
  • Assignments
  • Bangalore Branch

    #25, 2nd Main Road, Vijaya Bank Colony Extention, Bangalore

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