Verilog Programming Training for FPGA

Participants will gain a profound understanding of verilog syntax and the pivotal coding styles that resonate with efficient logic design. The training emphasizes writing verilog rtl hardware designs with a keen focus on best coding practices, ensuring robust and optimized outcomes. 

A meticulously crafted Verilog Programming Training for FPGA enthusiasts and professionals, positioning them at the forefront of modern logic design.

• Navigating deeper, learners will be enlightened on the synthesizable subset of VERILOG, coupled with the know-how of addressing problematic coding issues in hardware. The course curriculum further integrates essential skills like printing messages in testbenches and scripting transaction-based testbenches using subprograms. 
• With hands-on guidance on leveraging VERILOG simulation and synthesis tools, participants will be fully equipped to pioneer innovative FPGA solutions and drive excellence in their respective domains.

Certificate

• All participants will receive a Certificate of Completion from Tertiary Courses after achieved at least 75 percent attendance.

Day 1
FPGA Design FLOW

• Motivation

Topic 1 : Architecture of FPGA

• Introduction to Programmable logic device (PLD)
• Architecture
• Structure of PLD

Topic 2 : Introduction to Verilog

• Levels of Abstraction
• Syntax & Semantics
• Reserved Keywords

Topic 3: Verilog Ports

• Ports declaration
• Data types
• Physical
• Abstract
• Constant

Topic 4: Operators

• Arithmetic Operator
• Bit Wise
• Logical
• Reduction
• Shift
• Relational/Equality/Concatenation/Replication/Conditional

Topic 5: Modeling

• Data Flow
• Behavioral
• Structural

Topic 6: Timing Control

• Inertia Delay
• Transport Delay
• Event Control
• Back-Annotation

Topic 7 : Conditional statement

• If
• Nested if
• Case, casex, casez

Topic 8: User Define Primitives.

• Process statement / Sensitivity List

Topic 9: Lab Exercise

• Combinational Logic

Day 2

Topic 10: State Machine

• Mealy 
• Moore

Topic 11: Simulation

• Steps of simulation / Simulation Deltas
• Test bench

Topic 13: Lab Activities

• Design Entry
• Writing Verilog code 
• Test bench 
• Simulating Verilog code with Vivado (Xilinx)
• Synthesize the code

Job Roles

• Digital Ic Designers
• Vhdl/verilog Programmers
• Fpga Architects
• Embedded Design Engineers